The present invention relates to an arithmetic unit with a simple overflow detection system and, more particularly, to an arithmetic unit for performing arithmetic operations between first and second data in a fixed and floating decimal point operations and a logical address operation of a computer employing virtual memory system. The first data is exclusively divided into a fixed value portion and a variable portion whose digit position is lower than that of the fixed value portion. The digits contained in the fixed value portion and the variable portion are fixed and variable, respectively. The ratio of a length of the fixed value portion to that of the variable portion in the first data varies.
A typical conventional arithmetic unit of this type is illustrated in FIG. 1. First data has a 32-bit length and consists of mode 1 data, mode 2 data, and mode 3 data. The mode 1 data consists of an 8-bit fixed value portion and a 24-bit variable portion. The mode 2 data consists of 16-bit fixed value and variable portions. The mode 3 data consists of only a 32-bit variable portion. Second data consists of a variable portion, the bit length of which is the same as that of the variable portion of the first data. The arithmetic unit of FIG. 1 includes: a mode register 1 for outputting a mode signal corresponding to an externally designated data mode; input registers 2 and 3 for storing the first and second data and outputting them in response to an addition instruction; an adder 4 for adding output data A1 and B1 of the upper eight bits from the input registers 2 and 3; an adder 5 for adding data A2 and B2 of lower 8 bits of data A1 and B1 of the input registers 2 and 3; an adder 6 for adding data A3 and B3 of the lowest 16 bits from the input registers 2 and 3; a switch circuit 7 for supplying data zero ("0") to the adder 4 when the mode signal from the mode register 1 represents mode 1 or 2, and the data B1 from the input register 3 to the adder 4 when the mode signal represents mode 3; a switch circuit 8 for supplying data "0" to the adder 5 when the mode signal represents mode 2, and the data B2 from the input register 3 to the adder 5 when the mode signal represents mode 1 or 3; a switch circuit 9 for outputting a carry signal C2, C3, or C1 from the adder 5, 6, or 4 when the mode signal represents mode 1, 2, or 3; a carry cutoff circuit 10 for inhibiting the supply of the carry signal C2 from the adder 5 to the adder 4 when the mode signal represents mode 1; a carry cutoff circuit 11 for inhibiting the supply of the carry signal C3 from the adder 6 to the adder 5 when the mode signal represents mode 2; and an output register 12 for linking the outputs from the adders 4, 5, and 6 and outputting the sum as an arithmetic operation result.
With the arrangement described above, a plurality of adders of different, short bit lengths must be used to correspond with the bit lengths of the fixed value and variable portions of different types of input data. In carry lookahead control, carry delay times for carry matching of the respective adders are increased. These adders and the carry cutoff circuits complicate the circuit arrangement of the conventional arithmetic and logic unit.